1. Technical Field
The present application relates generally to semiconductor devices and includes methods and structures for improving the fabrication of semiconductor devices such as 3D memory structures.
2. Related Art
NAND flash memory is a nonvolatile memory that is used in a wide range of applications including mobile phones, digital cameras, and solid-state hard drives. The high storage density of NAND flash memory, especially when compared to NOR flash memory, has played a large role in its market penetration. This storage density is achieved in part through the use of strings of memory cells connected in series between a ground line and bit lines, which reduces the number of metal contacts required. These strings are commonly called “NAND strings” due to their resemblance to NAND gates. Each memory cell within a NAND string can be addressed by a word line that the memory cell shares with neighboring cells of other NAND strings. In the past, NAND flash memory has been implemented as a two-dimensional (planar) array defined by word lines and bit lines that intersect perpendicularly, with the memory cells being formed at those intersections.
The NAND string topology has been further developed to achieve still greater storage density. Such efforts have lead to the development of three-dimensional (3D) NAND flash memory, in which memory cells are stacked vertically on top of one another.
Recent developments include forming three-dimensional (3D) semiconductor devices using thin film transistor (TFT) techniques applied to charge trapping memory techniques, and cross-point array techniques applied for anti-fuse memory. In respect to the latter, multiple layers of word lines and bit lines are provided with memory elements at their respective cross-points. Developments also include forming vertical NAND cells using charge-trapping memory technology, in which a multi-gate field effect transistor structure having a vertical channel operating like a NAND gate uses silicon-oxide-nitride-oxide-silicon (SONOS) charge trapping technology to create a storage site at each gate/vertical channel interface. In respect to the latter, recent developments have improved the size and manufacturing costs for three-dimensional semiconductor devices by forming stacks of strips of conductive material separated by insulating material and providing memory elements in interface regions between conductive materials of the stacks.
FIG. 1 shows a schematic diagram illustrating a 3D NAND Flash array structure. This figure shows a partial VG device as an example, which includes a string select line (SSLn) 10, a global select line (GSL) 11, channels 12, source line (SL) 17, source lines (SSLn) 18, source contacts 20, metal line 21, bit lines 31, 32, 33, and bit line contacts 41, 42, 43, arranged in 3D fashion. The string select lines (SSLn) 10 and the global select lines (GSL) 11 may include additional silicide layer on top of poly plugs to reduce the overall resistance.